Power Consumption Model at Functional Level for VLIW Digital Signal Processors

Publication Type:

Conference Paper


DASIP'08 Conference on Design and Architectures for Signal and Image Processing (2008)


In this contribution the modeling of power consumption for the VLIW processor TMS320C6416T is presented taking into account typical software algorithms in signal processing. The modeling is performed at the functional level making this approach distinctly different from other modeling approaches in low level technique. This means that the power consumption can be identified at an early stage in the design process, enabling the designer to explore different hardware architectures and algorithms. Some typical signal processing algorithms are used for the purpose of validating the proposed model. The estimated power consumption is compared to the physically measured power consumption, achieving a very low resulting average estimation error of 1.75% and a maximum estimation error of only 3.6%.